1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, it relates to an integrated circuit (IC) device of a compound semiconductor and a method for producing the same. The present invention also relates to an improvement of the isolation of active elements (i.e. active regions) from each other in the compound semiconductor IC device.
2. Description of the Related Art
In silicon semiconductor IC devices it is necessary to form an isolation region or structure such as a PN junction, or insulating layer. In general, there has been no special need to form an isolation region in GaAs FET IC devices, since a channel region, source region, and drain region of each GaAs FET are formed in a semi-insulating GaAs substrate by an ion-implantation method. Recently, however, IC devices, such as FETs utilizing a two-dimensional electron gas and heterojunction bipolar transistors, are produced by using a laminated layer structure formed on a substrate by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). In this case, it is necessary to form an isolation region in the laminated layer so as to isolate the active elements (regions) from each other. Such an isolation can be achieved by etching portions of the laminated layer between active regions thereof so as to form island active regions (e.g., cf. FIG. 1 of U.S. Ser. No. 676,359 filed on Nov. 29, 1984, corresponding to EP-A-0143656). In this type of isolation, steps formed by etching tend to cause breaking of interconnection conductor (i.e., a so-called step-coverage failure), and a base area of each island (i.e. active region is increased, preventing an increase in integration degree.
Isolation can be also achieved by implanting ionse, such as hydrogen (H.sup.+) and oxygen (O.sup.+) into portions of the laminated layer except for the active regions, to make those portions inactive (e.g., cf. FIG. 10 of U.S. Ser. No. 587,967 filed on March 9, 1984, corresponding to EP-A-0119089). In this type of isolation, the resistivity of the isolation region is reduced by a heat-treatment carried out in a later production step. During the heat-treatment, the introduced ions diffuse and increase the area of the isolation region, also preventing an increase in integration degree. It is difficult to carry out a deep inactivation by the ion-implantation method. Especially where oxygen ions are implanted, carriers trapped at a gap center are apt to be excited when an electric field is applied to the ion-introduced region, so that a current may flow
Furthermore, it is possible for isolation to be achieved by a combination of etching and filling, namely, etching a portion of the laminated layer around the active regions to form a U-shaped or V-shaped groove and filling the groove with an insulating material, such as SiO.sub.2, Si.sub.3 N.sub.4, and polycrystalline silicon. Such a combination process is adopted, for example, in a V-groove Isolation Polycrystal backfill structure (VIP), and in a U-groove isolation structure (wherein the U-groove is formed by a reactive ion etching (RIE) and filled with the insulating material), for silicon IC devices. However, where the U-shaped or V-shaped groove is formed in the laminated layer of the GaAs IC devices and is filled with SiO.sub.2, Si.sub.3 N.sub.4 and the like, the difference in the thermal expansion coefficient between GaAs and SiO.sub.2 (Si.sub.3 N.sub.4) produces an internal stress which may cause cracks during a heat-treatment. The thermal expansion coefficients of GaAs, SiO.sub.2, and Si.sub.3 N.sub.4 are 8.7.+-.0.1.times.10.sup.-6 (1/K), 5 to 6.times.10.sup.-7 (1/K), and 3 to 5.times.10.sup.-6 (1/K), respectively. In this case, when GaAs is etched in the later step, the filled insulating material is not etched, so that a step is formed at the end of the isolation region. Such a step may bring about a step-coverage failure of an interconnection conductor.